Design and Applications of Emerging Computer Systems

Logarithmic Floating-point Multipliers for Efficient Neural Network Training.- Part-IV. Quantum Computing and Other Emerging Computing.- Chapter 22. Cryogenic CMOS for quantum computing.- Chapter 23. Memristive Crossbar System towards Hardware Accelaration of Quantum Algorithms.- Chapter 24. A Review of Posit Arithmetic for Energy Efficient Computation: Methodologies, Applications, and Challenges.- Chapter 25. Designing Fault Tolerant Digital circuits in Quantum-dot Cellular Automata.- Chapter 26. CMOS Circuit-based Fully Connected Ising Machines with Parallel Updating and Its Applications in MIMO Detection .- Chapter 27. Approximate Communication in Network-on Chips for Training and Inference of Image Classification Models.

He is the Vice President-Elect for TA of the IEEE Nanotechnology Council (NTC). He has served as a Steering Committee Chair of IEEE Transactions on VLSI Systems, Associate Editors of IEEE Transactions on Circuits and Systems I: Regular Paper, IEEE Transactions on Emerging Topic in Computing and Computers, IEEE Transactions on Computers, IEEE Open Journal of Computer Society and IET Computers & Digital Techniques, a Guest Editor of Proceedings of the IEEE and IEEE Nanotechnology Magazine, the member of IEEE Symposium on Computer Arithmetic (ARITH) Steering Committee Member, 2020 TETC and AsianHOST 2021 Best Paper Award Committee. He is the Program Co-Chair of IEEE ARITH 2020, 17th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2022) and IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2023), and program members for a number of international conferences including DAC, ARITH, DATE, ASP-DAC, ISCAS, ASAP, ISVLSI, ICCD, GLSVLSI, AsianHOST, NANORACH, AICAS, SiPS, NMDC et al. He is a tutorial organizer and speaker in DAC 2022, DATE 2022, IEEE ISCAS 2021 and COINS 2021. He is a member of both Circuits & Systems for Communications (CASCOM) Technical Committee and VLSI Systemsand Applications (VSA) Technical Committee, IEEE Circuits and Systems Society. He is a Senior Member of the IEEE, CIE and CCF.

 

Dr. Jie Han received the B.Sc. degree in electronic engineering from Tsinghua University, Beijing, China, in 1999 and the Ph.D. degree from the Delft University of Technology, The Netherlands, in 2004. He is currently a Professor and Director of Computer Engineering in the Department of Electrical and Computer Engineering at the University of Alberta. His research interests include approximate computing, stochastic computing, brain-inspired learning systems and neural networks, reliability and fault tolerance, nanoelectronic circuits and systems, novel computational models for learning and biological applications.

Dr. Han was a recipient of the Best Paper Awards at the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2015) and the Automation and Test in Europe Conference (DATE 2023), as well as four Best