Emerging Technology and Architecture for Big-data Analytics

Part I State-of-the-Art Architectures and Automation for Data-analytics.- Chapter 1. Scaling the Java Virtual Machine on a Many-core System.- Chapter 2.Scaling the Java Virtual Machine on a Many-core System.- Chapter 3.Least-squares based Machine Learning Accelerator for Big-data Analytics in Smart Buildings.- Chapter 4.Compute-in-memory Architecture for Data-Intensive Kernels.- Chapter 5. New Solutions for Cross-Layer System-Level and High-Level Synthesis.- Part II New Solutions for Cross-Layer System-Level and High-Level Synthesis.- Chapter 6.Side Channel Attacks and Efficient Countermeasures on Residue Number System Multipliers.- Chapter 7. Ultra-Low-Power Biomedical Circuit Design and Optimization: Catching The Don't Cares.- Chapter 8.Acceleration of MapReduce Framework on a Multicore Processor.- Chapter 9. Adaptive dynamic range compression for improving envelope-based speech perception: Implications for cochlear implants.- Part III Emerging Technology, Circuits and Systems for Data-analytics.- Chapter 10. Emerging Technology, Circuits and Systems for Data-analytics.- Chapter 11. Energy Efficient Spiking Neural Network Design with RRAM Devices.- Chapter 12. Efficient Neuromorphic Systems and Emerging Technologies - Prospects and Perspectives.- Chapter 13. In-memory Data Compression Using ReRAMs.- Chapter 14. In-memory Data Compression Using ReRAMs.- Chapter 15.Data Analytics in Quantum Paradigm - An Introduction.

Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2002 and 2008 respectively. From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen, Germany as a Junior Professor. Since September, 2014, he is appointed as an assistant Professor in SCE, NTU. During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was commercialized later by a leading EDA vendor. He developed several high-level optimizations and verification flow for embedded processors. In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. Together with his doctoral students, he proposed domain-specific high-level synthesis for cryptography, high-level reliabilityestimation flows, generalization of classic linear algebra kernels and a novel multi-layered coarse-grained reconfigurable architecture. In these areas, he published as a (co)-author over 80 conference/ journal papers, several book-chapters and a book. Anupam served in several TPCs of top conferences, regularly reviews journal/ conference articles and presented multiple invited seminars/tutorials in prestigious venues. He is a member of ACM and a senior member of IEEE.

Chang Chip Hong received his B.Eng. (Hons) from National University of Singapore in 1989, and his M.Eng. and Ph.D. from the School of Electrical and Electronic Engineering of Nanyang Technological University, Singapore in 1993 and 1998, respectively. Since 1999, he has been with the School of Electrical and Electronic Engineering, Nanyang Technological University where he is currently an Associate Professor. He holds concurrent appointments at the university as the Assistant Chair (Alumni) of the School of EEE since